The threshold voltage is a key parameter of an MOS transistor. In an electronic circuit, transistors with different threshold voltages are generally required because transistors do not all have the same functions and must offer different performance. For example, some transistors in a circuit have a high threshold voltage and thus a low “blocked” state current (low-consumption transistors) whereas others have a low threshold voltage and thus a high “passing” state current (high-performance transistors). Different families of transistors are therefore used in circuit design. These transistors are produced on bulk silicon (Si), silicon on insulator (SOI) or silicon on nothing (SON), as described in the paper “Silicon-on-Nothing MOSFETs: Performance, Short-Channel Effects, and Backgate Coupling” by Jérémy Pretet et al, IEEE Transactions on Electron Devices, Vol. 51, No. 2, February 2004.
The threshold voltage generally depending on the doping of the channel of the transistor, differently implanted transistor channels are generally used. Another technique, known as the fully depleted (FD) technique, is used to produce transistors on undoped films. This technique may be used on SOI, as described in the paper “Threshold Voltage of Thin-Film Silicon-on-Insulator (SOI) MOSFETs” by Kyung-Kyu LIM et al., IEEE Transactions on Electron Devices, Vol. ED-30, No. 10, October 1983. This technique is referred to as the FDSOI (fully-depleted SOD or SON technique. It provides better electrostatic control, reduced variability and increased mobility. In this case, the threshold voltage is essentially dependent on the output work of the gate of the transistor (and little dependent on the doping).
Accordingly, to obtain different threshold voltages in this architecture, one solution is to co-integrate gates with different output works. This approach has numerous drawbacks. Adjusting the output work of the gates and the co-integration remains a real technological and physical challenge. Adjusting the threshold voltages in FD devices generally also remains a major challenge blocking their further development.
An MOS transistor with adjustable threshold voltage is known from the document European Patent Publication No. EP 0 409 697. In that document, a floating gate transistor has a threshold voltage that is adjusted continuously by trapping. Compared to the usual floating gate structure, the tunnel oxide in the above document is thinned above the drain to facilitate programming. However, in this case, the gate stack must at one and the same time be compatible with memory applications and logic applications, which is difficult to achieve. In logic applications, there is a benefit in increasing the gate/channel coupling (by reducing the thickness of the gate oxide), whereas in memory applications, a minimum tunnel oxide size must be maintained to guarantee good retention. The oxide is therefore necessarily thick, which is not the optimum for logic transistors.
There is also known the document by H. Silva and S. Tiwari “A Nanoscale Memory and Transistor Using Backside Trapping”, IEEE Trans. on Nanotechnology Vol. 3 No. 12 June 2004. In that document, the threshold voltage of the transistor is modulated by trapping in the buried insulation and by capacitive coupling. The threshold voltage is always modulated under the same (binary) conditions. The curves in the above document are typical of the memory application, in terms of endurance and retention time.
The corresponding U.S. Pat. No. 7,057,234 concerns the structure: silicon nanocrystals are referred to as possible trapping sites. The above document indicates the use of this structure either for transistors in logic mode or for memory points, which modes are distinguished by different bias sets. The above document proposes to use the trapping mechanism for memory points only.
Thus the above document does not relate in any way to producing transistors with an adjustable threshold voltage, and notably transistors in which the threshold voltage is intentionally adjusted as a function of the logic or analog target application of the transistor (low threshold voltage transistor, standard threshold voltage transistor or high threshold voltage transistor).
Thus there is at present no technological solution that makes it possible to produce FD transistors that are optimized, notably from an electrostatic point of view (and more particularly for short channels) and simultaneously have a threshold voltage that is adjustable as a function of the intended logic or analog application of the transistor.